- Analog/mixed-signal integrated circuits design
Co-advised by Prof. Yusuf Leblebici
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Cosimo Aprile was born in Leverano, Italy in 1988. He received the bachelor degree in Electronic Engineering in July 2010 from Politecnico di Torino. During the third academic year (2009/2010) he studied at Institut National des Sciences Appliquées de Lyon (INSA) in France.
He received the international M.Sc. in Micro and Nanotechnologies for ICTs which is a double degree between the Politecnico di Torino (Polito) and Institut National Polytechnique de Grénoble (INPG) and a joint degree with the École polytechnique fédérale de Lausanne (EPFL).
From March 2012 up to March 2013 he was employed by IBM Zurich Research Laboratory. In this period he worked for the Master Thesis project under the supervision of Professor Leblebici (EPFL) and Doct. Thomas Toifl (IBM). The task was the design of a low power receiver in 32nm SOI-CMOS able to efficiently remove far end crosstalk in single ended wireline communication systems.
|Home > A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS|
A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7x8-tap cross decision feedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER< 10^-12 with 12.5%UI margin. It occupies 300x350um2 with an energy efficiency of 5.9mW/Gb/s.
- Fulltext: VLSI15_1 - PDF;
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